1. Field of the Invention
The present invention relates to a semiconductor device including a protection circuit. More specifically, the present invention relates to an integrated circuit device including an AC trigger break (cut-off) type thyristor for protecting a semiconductor integrated circuit from breakdown by electrostatic discharge (ESD).
2. Description of the Related Art
Usually, an integrated circuit device is provided with an electrostatic discharge protection circuit (hereinafter, referred to as ESD protection circuit) for protecting a semiconductor integrated circuit from breakdown by electrostatic discharge. (For example, see Christian C. Russ et al., “GGSCRs: GGNMOS Triggered Silicon Controlled Rectifiers for ESD protection in Deep Sub-Micron CMOS Processes”, ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS 2001 (23rd).)
FIG. 9 shows the basic configuration of an integrated circuit device provided with a conventional ESD protection circuit. As shown in FIG. 9, the protection target, that is, a semiconductor integrated circuit (protection target device) 20 is connected between a power supply terminal (power supply PAD) 11 and a ground terminal (GDN-PAD) 12. An ESD protection circuit 30 and a protection diode 40 are connected in parallel with the semiconductor integrated circuit 20 between the power supply PAD 11 and the GDN-PAD 12. A power supply interconnect (wiring) resistance R1 and a ground interconnect (wiring) resistance R2 are interposed between the semiconductor integrated circuit 20 and the ESD protection circuit 30.
The ESD protection circuit 30 discharges positive ESD surge current supplied between the power supply PAD 11 and the GND-PAD 12 based on the GND-PAD 12. The protection diode 40 discharges negative ESD surge current.
FIG. 10 shows the configuration of the conventional ESD protection circuit 30. Here, an AC trigger break-type thyristor is given as one example. In this case, the ESD protection circuit 30 is composed of CR integrating circuit 31, trigger circuit 32 and thyristor 33.
In the CR integrating circuit 31, a resistance element (R) 31a is an N-well resistor having a resistance value of 1 MΩ, which is formed on a P type semiconductor substrate (33-1). A capacitance element (C) 31b is a MOS (Metal Oxide Semiconductor) capacitor having a capacitance value of 6 pF. One terminal of the CR integrating circuit 31 comprising two elements 31a and 31b, that is, one terminal of the resistance element 31a is connected to the power supply PAD 11. The other terminal of the resistance element 31a is connected to one terminal (one electrode) of the capacitor element 31b. The other terminal of the CR integrating circuit 31, that is, the other terminal (the other electrode) of the capacitor element 31b is connected to the GND-PAD 12. A connection point between the resistance element 31a and the capacitor element 31b, that is, an output terminal (intermediate terminal) of the CR integrating circuit 31 is connected to an input terminal of the trigger circuit 32.
The trigger circuit 32 comprises a CMOS (Complementary MOS) structure inverter circuit composed of P-channel MOS (PMOS) and N-channel MOS (NMOS) transistors 32a and 32b. The source of the PMOS transistor 32a is connected to the power supply PAD 11. The source of the NMOS transistor 32b is connected to the GND-PAD 12. Each gate (input terminal) of PMOS and NMOS transistors 32a and 32b is connected with the output terminal of the CR integrating circuit 31. The output terminal of the trigger circuit 32 in which each drain of PMOS and NMOS transistors 32a and 32b is commonly connected is connected to the thyristor 33.
The PMOS transistor 32a has gate width (W) of 40 μm, gate length (L) of 0.2 μm, gate oxide film thickness (Tox) of 3 nm and threshold voltage (Vth) of −0.4 V. On the other hand, the NMOS transistor 32b has gate width (W) of 20 μm, gate length (L) of 0.2 μm, gate oxide film thickness (Tox) of 3 nm and threshold voltage (Vth) of 0.4 V.
The thyristor 33 is composed of PNP transistor 33a, NPN transistor 33b and resistance element 33c. In the thyristor 33, the output terminal of the trigger circuit 32 is connected with the collector of the PNP transistor 33a, the base of the NPN transistor 33b and one end of the resistance element 33c. The emitter of the PNP transistor 33a is connected to the power supply PAD 11 while the base thereof being connected to the collector of the NPN transistor 33b. The emitter of the NPN transistor 33b and the other end of the resistance element 33c are connected to the GND-PAD 12.
FIG. 11 shows the actual device structure of the thyristor 33. For example, the surface of a P type semiconductor substrate 33-1 is formed with an N-well region 33-2. The N-well region 33-2 has a peak concentration of 3.5×1017 cm−3 and a junction depth (Xj) of 1.5 μm. The surface of the P type semiconductor substrate 33-1 is further formed with a P-well region 33-3 adjacent to the N-well region 33-2. The P-well region 33-3 has a peak concentration of 6.0×1017 cm−3 and the same depth (Xj=1.5 μm) of impurity concentration as the P type semiconductor substrate 33-1. In addition, the surface of a P type semiconductor substrate 33-1 is selectively formed with several isolation insulating regions 33-4 having STI (Shallow Trench Isolation) structure.
The surface of the N-well region 33-2 excluding the insulating region 33-4 is formed with a P+ layer 33-5 having a peak concentration of 1×1020 cm−3 and a junction depth (Xj) of 0.18 μm. The surface of the P-well region 33-3 excluding the insulating region 33-4 is formed with an N+ layer 33-6 and a P+ layer 33-7. The N+ layer 33-6 has a peak concentration of 1×1020 cm−3 and a junction depth (Xj) of 0.18 μm. The P+ layer 33-7 has a peak concentration of 1×1020 cm−3 and the same depth (Xj=0.18 μm) of impurity concentration as the P type semiconductor substrate 33-1. The surface of the P type semiconductor substrate 33-1, that is, the region forming neither N-well nor P-well region 33-2 and 33-3 is formed with a P+ layer 33-8. The P+ layer 33-8 has a peak concentration of 1×1020 cm−3 and the same depth (Xj=0.18 μm) of impurity concentration as the P type semiconductor substrate 33-1.
In the thyristor 33, the foregoing P+ layer 33-5, N-well region 33-2 and P-well region 33-3 function as the emitter, base and collector of the PNP transistor 33a shown in FIG. 10, respectively. In FIG. 11, Ln denotes the base length of the PNP transistor 33a; in this case, the base length is about 0.4 μm. The P+ layer 33-5 is connected with the power supply PAD 11.
Likewise, the foregoing N-well region 33-2, P-well region 33-3 and N+ layer 33-6 function as the collector, base and emitter of the NPN transistor 33b shown in FIG. 10, respectively. In FIG. 11, Lp denotes the base length of the NPN transistor 33b; in this case, the base length is about 0.4 μm. The N+ layer 33-6 is connected with the GND-PAD 12 while being connected to the P+ layer 33-7 and the output terminal of the trigger circuit 32 via a 5 KΩ N-well resistor equivalent to the resistance element 33c shown in FIG. 10.
As is evident from FIG. 11, the P+ layer 33-7 is connected to the P+ layer 33-8 connected to the GND-PAD 12 via the P-well region 33-3 and the P type semiconductor substrate 33-1 However, the resistance value of the P type semiconductor substrate 33-1 occupying most of the connection resistance has large variations depending on the manufacture process. In order to stabilize the resistance value of the P type semiconductor substrate 33-1, the resistance element 33c is arranged. High concentration diffusion layers, that is, P+ layer 33-5, P+ layer 33-7, P+ layer 33-8 and N+ layer 33-6 have the width of about 1 μm and the length (the depth dimension in paper) of about 80 μm.
As seen from FIG. 10, the thyristor 33 has two current paths. More specifically, the thyristor 33 has a first path from the base of the PNP transistor 33a to the collector of the NPN transistor 33b, and a second path from the collector of the PNP transistor 33a to the base of the NPN transistor 33b. In fact, the first and second paths are one path ranging from the N-well region 33-2 to the P-well region 33-3. For this reason, it is impossible to insert elements to either of the first and second paths.
The operation of the ESD protection circuit 30 having the foregoing configuration will be explained below with reference to FIG. 10. First, the operation (protection operation) when ESD surge voltage is applied will be described. For example, a positive ESD surge voltage is applied between the power supply PAD 11 and the GND-PAD 12. Whereupon the trigger circuit 32 and the thyristor 33 are in an operating state by the voltage (Vdd) supplied from the power supply PAD 11. In addition, the output (intermediate node) CR integrating circuit 31 is held to GND potential (0 V) by the function of the capacitor element 31b. By doing so, the PMOS transistor 32a of the trigger circuit 32 is in a conductive state. Therefore, the current from the power supply PAD 11 flows through the base-emitter junction of the NPN transistor 33b of the thyristor 33. As a result, the NPN transistor 33b becomes-on state. In other words, a collector current flows through the NPN transistor 33b. 
By the collector current, current flows through the base of the PNP transistor 33a, and thereby, the PNP transistor 33a becomes on state. The collector current of the PNP transistor 33a supplies base current of the NPN transistor 33b. Thus, positive feedback loop is formed. As a result, since the thyristor 33 causes snap back, the ESD protection circuit 30 becomes low impedance state capable of carrying large current from the power supply PAD 11 toward the GND-PAD 12. Therefore, the ESD surge current is discharged without stepping up the voltage from the power supply PAD 11. Consequently, there is no possibility that the semiconductor integrated circuit 20 is broken by the ESD surge current.
The normal operation (non-protection operation) of the ESD protection circuit 30 will be explained below. In a state that the voltage (Vdd) from the power supply PAD 11 has no change, the intermediate node of the CR integrating circuit 31 has voltage Vdd by the function of the resistance element 31a. Thus, the output of the trigger circuit 32 is GND potential (0 V); therefore, the NPN transistor 33b becomes off state. In this case, no base current of the PNP transistor 33a is supplied; therefore, no current flows through the PNP transistor 33a. In other words, the thyristor 33 is intactly in the cut-off state.
FIG. 12 is a graph showing the I-V characteristics of the large current region of the conventional ESD protection circuit 30. The ordinate Iesd is the maximum current value of the ESD surge current carried from the power supply PAD 11.
The ESD protection circuit 30 protects the semiconductor integrated circuit 20 from the breakdown by electrostatic discharge. In other words, this means preventing the gate oxide film of MOS integrated circuit from being broken down by the ESD surge current. In order to perform the foregoing protection, the following conditions are given. The current I from the power supply PAD 11 is set within a range smaller than the maximum current value Iesd, and the voltage V does not exceed the oxide film breakdown voltage BVox (Vclamp<BVox). In order to prevent the thyristor 33 from latching up by well induction in the normal operation, the voltage minimum value Vh after snap back must be set larger than the maximum guaranteed power-supply voltage Vddmax (normally, 1.1*Vdd) (Vh>Vddmax). Therefore, an on-resistance (required resistance value) Ron the thyristor 33 must have in conductive state after snap back is given:Ron=(Vclamp−Vh)/(Iesd−Ih)where, Ih is current at the point (Vh) where voltage is minimal after snap back. In general, Iesd>>Ih; thus, the following equation (1) is obtained.Ron≈(Vclamp−Vh)/Iesd  (1)
In addition, the following relations are given.Vclamp<BVox  (2)Vh>Vddmax  (3)
From the foregoing equations (1), (2) and (3), the following equation is obtained.Ron<(BVox−Vddmax)/Iesd
For simplification, man-machine model such that the maximum current value Iesd is 2.7 A is given as one example. In micro CMOS devices having an oxide film thickness of about 12 angstroms, the oxide film breakdown voltage BVox is about 4 V.
That is, if Vddmax is equal to 1.2 V, the required resistance value is as follows.Ron<(4 V−1.2 V)/2.7 A=1.0 Ω
In order to realize the required resistance value, the device width (high concentration diffusion layer length) shown in FIG. 11 requires 80 μm in the conventional ESD protection circuit 30. As a result, the circuit has a huge size.
With the scale-down of MOS integrated circuits, the power supply voltage is set low, and the oxide film thickness is thinned. On the other hand, the required resistance value (Ron) is reduced with thinning of the gate oxide film. In order to realize a predetermined required resistance value (Ron), the ESD protection circuit 30 must be formed into a huge size more and more.
In addition, the interconnect resistances R1 and R2 are interposed between the semiconductor integrated circuit 20 and the ESD protection circuit 30, as illustrated in FIG. 9. In this case, both terminals of the semiconductor integrated circuit 20 further steps up.
The condition for protecting the oxide film in the foregoing case is as follows.Vclamp+Iesd*(R1+R2)<BVox
In other words, the following equation (4) is given.Vclamp<BVox−Iesd*(R1+R2)  (4)
In this case, the following equation is given.Ron+R1+R2<(BVox−Vddmax)/Iesd
Considering interconnect resistances R1 and R2, the required resistance value (Ron) must be made further small; for this reason, the ESD protection circuit 30 is formed into a huge size more and more. Otherwise, many ESD protection circuit 30 must be interposed between the power supply PAD 11 and the GND-PAD 12 in order to make small the value of the interconnect resistances R1 and R2.
As described above, the gate oxide film must be thinned, and the required resistance value (Ron) must be made small in accordance with the interconnect resistances in the conventional case. For this reason, there is a problem that the ESD protection circuit is formed into a huge size.